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Ordering number : ENN*6728
CMOS IC
LC651154N, 651154F, 651154L, LC651152N, 651152F, 651152L
Four-Bit CMOS Microcontrollers for Small-Scale Control Applications
Preliminary Overview
The LC651154N/F/L and the LC651152N/F/L are the small-scale control application versions of Sanyo's LC6500 series of 4-bit single-chip CMOS microcontrollers, and feature the same basic architecture and instruction set. These microcontrollers include an 8input 8-bit A/D converter and are appropriate for use in a wide range of applications, from applications with a small number of circuits and controls that were previously implemented in standard logic to applications with a larger scale such as home appliances, automotive equipment, communications equipment, office equipment, and audio equipment such as decks and players. Also note that since these ICs provide the same basic functions (certain functions and specifications do differ) as, and are pin compatible with the earlier LC651104N/F/L and LC651102N/F/L, they can replace those ICs in most cases. -- All ports: * Are I/O ports * I/O voltage handling capacity: 15 V (maximum) (Open-drain specification C, D, E, and F ports only) * Output current: 20 mA (maximum) sink current (Are capable of directly driving an LED.) -- Support options to match application system specifications A. Open-drain output, internal pull-up resistor specification: All ports, in bit units B. Output level at reset specification: Ports C and D can be specified to go to the high or low level in 4-bit units. Interrupt function -- Timer interrupts through an interrupt vector (Can be tested under program control) -- INT pin and serial I/O full/empty interrupts through an interrupt vector (Can be tested under program control) Stack levels: 8 (Shared with the interrupt system.) Timers: 4-bit variable prescaler and 8-bit programmable timers Clock oscillator options that match a wide range of system specifications -- Oscillator circuit options: Two-pin RC oscillator (N and L versions) Two-pin ceramic oscillator (N, F, and L versions) -- Clock divider circuit options: No divider, built-in divide-by-3, built-in divide-by-4 (N and L versions) Continuous square wave output (with a period 64 times the cycle time) A/D converter (successive approximation) -- 8-bit precision with 8 input channels Watchdog timer
*
Features
* Fabricated in a CMOS process for low power (A standby function that can be invoked under program control is also provided.) * ROM/RAM LC651154N/F/L -- ROM: 4K x 8 bits, RAM: 256 x 4 bits LC651152N/F/L -- ROM: 2K x 8 bits, RAM: 256 x 4 bits * Instruction set: The 80-instruction set common to the LC6500 family * Wide operating supply voltage range: 2.2 to 6.0 V (L versions) * Instruction cycle time: 0.92 s (F versions) * On-chip serial I/O function * Flexible I/O ports -- Number of ports: 6 ports with a total of 22 pins * * *
* * *
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
91799RM (OT) No. 6278-1/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L -- RC circuit time constant -- Optional watchdog timer reset function from an external pin Function Table
Parameter Memory ROM RAM Instructions Instruction set Table reference Interrupts Timers On-chip functions Stack levels Standby function Number of ports Serial port I/O voltage handling capability I/O ports Output current I/O circuit types Output level at reset Square wave output Minimum cycle time Characteristics Supply voltage Current drain Oscillator Other items Oscillator element Divider circuit option Package LC651154N/1152N 4096 x 8 bits (1154N) 2048 x 8 bits (1152N) 256 x 4 bits (1154/1152N) 80 Supported 1 external, 1 internal 4-bit variable prescaler + 8-bit timers 8 Standby mode entered by the HALT instruction supported 22 I/O port pins Input and output in 4 or 8 bit units 15 V max. 10 mA typ. 20 mA max. LC651154F/1152F 4096 x 8 bits (1154F) 2048 x 8 bits (1152F) 256 x 4 bits (1154/1152F) 80 Supported 1 external, 1 internal 4-bit variable prescaler + 8-bit timers 8 Standby mode entered by the HALT instruction supported 22 I/O port pins Input and output in 4 or 8 bit units 15 V max. 10 mA typ. 20 mA max. LC651154L/1152L 4096 x 8 bits (1154L) 2048 x 8 bits (1152L) 256 x 4 bits (1154/1152L) 80 Supported 1 external, 1 internal 4-bit variable prescaler + 8-bit timers 8 Standby mode entered by the HALT instruction supported 22 I/O port pins Input and output in 4 or 8 bit units 15 V max. 10 mA typ. 20 mA max.
Open drain (n-channel) and pull-up resistor output options can be specified in 1-bit units A high or low level output can be selected in port units (ports C and D only) Supported 2.77 s (VDD 3 V) 3 to 6 V 1.5 mA typ. RC (800/400 kHz typ.) Ceramic (400 k, 800 k, 1 MHz, 4 MHz) 1/1, 1/3, 1/4 DIP30S-D, MFP30S, SSOP30 Supported 0.92 s (VDD 2.5 V) 2.5 to 6 V 2 mA typ. Ceramic 4 MHz 1/1 DIP30S-D, MFP30S, SSOP30 Supported 3.84 s (VDD 2.2 V) 2.2 to 6 V 1.5 mA typ. RC (400 kHz typ.) Ceramic (400 k, 800 k, 1 MHz, 4 MHz) 1/1, 1/3, 1/4 DIP30S-D, MFP30S, SSOP30
Note: Recommendations for oscillator elements and oscillator circuit constants will be announced as the recommended circuits for these ICs are determined. Verify the progress of these developments periodically.
No. 6278-2/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L Differences between the LC651154N/1152N and the LC651104N/1102N. The table below lists the points that require care when converting an existing product that uses the LC651104N/1102N to use the LC651154N/1152N.
Parameter Pdmax (1) : DIP Allowable power dissipation Pdmax (2) : MFP Pdmax (3) : SSOP fCFOSC [OSC1, OSC2] Oscillator characteristics Ceramic oscillator Oscillator frequency 2-pin RC oscillator Oscillator frequency fMOSC [OSC1, OSC2] LC651154N/1152N 310 mW 220 mW 160 mW Oscillator frequency precision: within 2% Changes in the recommended oscillator constants (See table 1.) 800 kHz typ. (VDD = 3 to 6 V) Constants changed: Rext = 5.6 k 1 % Frequency variability (sample to sample): 587 to 1298 kHz 400 kHz typ. (VDD = 3 to 6 V) Frequency variability (sample to sample): 290 to 616 kHz Pull-up resistors Serial clock input clock cycle time A/D converter characteristics AV+ = VDD AV- = VSS Watchdog timer Cw = 0.047 5% F Rw = 680 1% k RI = 100 1% Package Ru [RES] tCKCY (1) [ SCK] Operating voltage Reference input current IRIF [AV+, AV-] 200 to 800 k (500 k typ.) min. 2.0 s VDD = 3 to 6 V 200 to 800 A (500 A typ.) Oscillator frequency precision: within 4% LC651104N/1102N 250 mW 150 mW (No corresponding package)
900 kHz typ. (VDD = 4 to 6 V) Constants changed: Rext = 4.7 k 1 % Frequency variability (sample to sample): 634 to 1278 kHz 400 kHz typ. (VDD = 3 to 6 V) Frequency variability (sample to sample): 276 to 742 kHz 300 to 700 k (500 k typ.) min. 3.0 s VDD = 4 to 6 V 75 to 300 A (150 A typ.)
VDD = 3 to 6 V DIP30S-D, MFP30S An SSOP30 version was added.
VDD = 4 to 6 V
DIP30S-D, MFP30S
Differences between the LC651154F/1152F and the LC651104F/1102F. The table below lists the points that require care when converting an existing product that uses the LC651104F/1102F to use the LC651154F/1152F.
Parameter Pdmax (1) : DIP Allowable power dissipation Pdmax (2) : MFP Pdmax (3) : SSOP Operating supply voltage Low-level input voltage Oscillator characteristics Ceramic oscillator Oscillator frequency Pull-up resistors A/D converter characteristics AV+ = VDD AV- = VSS Package Reference input current IRIF [AV+, AV-] Ru [RES] Operating voltage 200 to 800 k (500 k typ.) AD speed 1/1 : VDD = 3.5 to 6 V AD speed 1/2 : VDD = 3 to 6 V 200 to 800 A (500 A typ.) DIP30S-D, MFP30S An SSOP30 version was added. 300 to 700 k (500 k typ.) AD speed 1/1 : VDD = 4.5 to 6 V AD speed 1/2 : VDD = 4 to 6 V 75 to 300 A (150 A typ.) DIP30S-D, MFP30S VDD VIL(n) LC651154F/1152F 310 mW 220 mW 160 mW 2.5 to 6 V Specifications for VDD = 4 to 6 V The specifications for VDD = 2.5 to 6 V were added. LC651104F/1102F 250 mW 150 mW (No corresponding package) 4 to 6 V Specifications for VDD = 4 to 6 V
fCFOSC [OSC1, OSC2]
Oscillator frequency precision: within 2 %
Oscillator frequency precision: within 4 %
No. 6278-3/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L Differences between the LC651154L/1152L and the LC651104L/1102L. The table below lists the points that require care when converting an existing product that uses the LC651104L/1102L to use the LC651154L/1152L.
Parameter Pdmax (1) : DIP Allowable power dissipation Pdmax (2) : MFP Pdmax (3) : SSOP Operating supply voltage Oscillator characteristics Ceramic oscillator Oscillator frequency 2-pin RC oscillator Oscillator frequency Pull-up resistors Serial clock input clock cycle time A/D converter characteristics AV+ = VDD AV- = VSS Watchdog timer Package fMOSC [OSC1, OSC2] Ru [RES] tCKCY (1) [ SCK] Operating voltage Reference input current IRIF [AV+, AV-] 400 kHz typ. (VDD = 2.2 to 6 V) Frequency variability (sample to sample): 290 to 841 kHz 200 to 800 k (500 k typ.) min. 2.0 s VDD = 3 to 6 V 200 to 800 A (500 A typ.) VDD = 2.2 to 6.0 V DIP30S-D, MFP30S An SSOP30 version was added. 400 kHz typ. (VDD = 2.5 to 6 V) Frequency variability (sample to sample): 276 to 742 kHz 300 to 700 k (500 k typ.) min. 6.0 s VDD = 4 to 6 V 75 to 300 A (150 A typ.) VDD = 2.5 to 6.0 V DIP30S-D, MFP30S VDD fCFOSC [OSC1, OSC2] LC651154L/1152L 310 mW 220 mW 160 mW 2.2 to 6 V Oscillator frequency precision: within 2% Changes in the recommended oscillator constants (See table 1.) Oscillator frequency precision: within 4% LC651104L/1102L 250 mW 150 mW (No corresponding package) 2.5 to 6 V
Caution: Perform a full system evaluation and inspection after replacing the microcontroller.
No. 6278-4/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L Pin Assignment The pin assignment is the same for the DIP, MFP, and SSOP packages.
No. 6278-5/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L Pin Functions
OSC1, OSC2: Connections for the oscillator capacitor and resistor or ceramic element RES: PA0 to PA3: PC0 to PC3: PD0 to PD3: PE0 to PE3: PF0 to PF3: PG0 to PG3: Reset Common I/O ports A0 to A3 Common I/O ports C0 to C3 Common I/O ports D0 to D3 Common I/O ports E0 to E3 Common I/O ports F0 to F3 Common I/O ports G0 to G3 TEST: INT: SI: SO: SCK: IC testing. Interrupt request input Serial input Serial output Serial clock input output
AD0 to AD7: A/D converter analog inputs AV+, AV-: WDR: A/D converter reference voltage inputs Watchdog timer reset input
Note: Pins SI, SO, SCK, and INT are shared function pins also used as PF0:3.
System Block Diagram
RAM: F: WR: AC: ALU: DP: E: CTL: OSC: TM: STS:
Shared with port F Data memory Flag Working register Accumulator Arithmetic and logic unit Data pointer E register Control register Oscillator circuit Timer Status register
ROM: PC: INT: IR: I.DEC: CF, CSF: ZF, ZSF: EXTF: TMF:
Program memory Program counter Interrupt control Instruction register Instruction decoder Carry flag and carry save flag Zero flag and zero save flag External interrupt request flag Internal interrupt request flag
No. 6278-6/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L Development Support The following are provided for development with the LC651154 and LC651152. * User's manual See the "LC651104/1102 User's Manual." * Development tools manual See the "Four-Bit Microcontroller EVA86000 Development Tools Manual." * Software manual "LC65/66 Series Software Manual" * Development tools -- Program development (EVA86000 System) -- On-chip EPROM microcontroller for program evaluation Pin Functions
Symbol VDD VSS Number of pins 1 I/O -- -- Function Option At reset Handling when unused --
Power supply
-- (1) Two-pin RC oscillator or external clock (2) Two-pin ceramic oscillator (3) Divider option 1. No divider 2. Divide-by-3 3. Divide-by-4
--
OSC1
1
OSC2
1
* Connection for the RC circuit or ceramic oscillator element used for the system clock oscillator * Leave OSC2 open when an external clock input is used. Output
Input
--
--
PA0 to PA3/ AD0 to AD3
4
I/O
* I/O port A0 to A3 Input in 4-bit units (IP instruction) Output in 4-bit units (OP instruction) Testing in 1-bit units (BP and BNP instructions) Set and reset in 1-bit units (SPB and RPB instructions) * PA3 is used for standby mode control * Application must assure that chattering does not occur on the PA3 input during HALT instruction execution. * All four pins have shared functions PA0/AD0 - A/D converter input AD0 PA1/AD1 - A/D converter input AD1 PA2/AD2 - A/D converter input AD2 PA3/AD3 - A/D converter input AD3 * I/O port C0 to C3 The port functions are identical to those of PA0 to PA3. (See note.) * The output during a reset can be selected to be either high or low as an option. Note: This port has no standby mode control function. * I/O port D0 to D3 The port functions and options are identical to those of PC0 to PC3.
(1) Open-drain output (2) Pull-up resistor Options (1) and (2) can be specified in bit units
High-level output (The output nchannel transistors in the off state.)
Select the open-drain output option and connect to VSS.
PC0 to PC3
4
I/O
(1) (2) (3) (4)
Open-drain output Pull-up resistor High-level output during reset Low-level output during reset * Options (1) and (2) can be specified in bit units * Options (3) and (4) are specified 4 bits at a time
* High-level output * Low-level output (Depending on option selected.) The same as PC0 to PC3 The same as for PA0 to PA3
PD0 to PD3
4
I/O
The same as PC0 to PC3
The same as for PA0 to PA3
Continued on next page.
No. 6278-7/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Continued from preceding page.
Symbol Number of pins I/O * I/O port E0 to E1 Input in 4-bit units (IP instruction) Output in 4-bit units (OP instruction) PE0-PE1/ WDR Set and reset in 1-bit units (SPB and RPB instructions) Testing in 1-bit units (BP and BNP instructions) * PE0 also has a continuous pulse (64*Tcyc) output function. * PE1 becomes the watchdog reset pin WDR when selected for such as an option. * I/O port F0 to F3 The port functions and options are identical to those of PE0 to PE1 (See note.) * PF0 to PF3 have shared functions as the serial interface pins and the INT input. PF0/SI PF1/SO PF2/SCK PF3/INT 4 I/O The function can be selected under program control. SI ... Serial input pin SO ... Serial output pin SCK ... Input and output of the serial clock signal INT ... Interrupt request input The serial I/O function can be switched between 4bit and 8-bit transfers under program control. Note: There is no continuous pulse output function. * I/O port G0 to G3 The port functions and options are identical to those of PE0 to PE1 (See note.) Note: There is no continuous pulse output function. PG0-PG3/ AD4-AD7 4 I/O * All four pins have shared functions. PG0/AD4 - A/D converter input AD4 PG1/AD5 - A/D converter input AD5 PG2/AD6 - A/D converter input AD6 PG3/AD7 - A/D converter input AD7 AV+ AV- 1 1 -- -- A/D converter reference voltage input * System reset input RES 1 Input * Applications must provide an external capacitor for the power-on reset. * Apply a low level to this pin for 4 clock cycles to effect and reset start. * IC test pin TEST 1 Input This pin must be connected to VSS during normal operation. -- -- This pin must be connected to VSS. -- -- -- -- -- Connect to VSS. Identical to those for PA0 to PA3 Identical to those for PA0 to PA3 Identical to those for PA0 to PA3 Identical to those for PA0 to PA3 Identical to those for PA0 to PA3 The serial port Identical to functions are those for PA0 disabled. to PA3 The interrupt source is set to INT. (1) Open-drain output (2) Pull-up resistor * Options (1) and (2) can be specified in bit units (3) Normal port PE1 (4) Watchdog reset WDR * Either options (3) and (4) may be specified. High-level output (The output nchannel transistors in the off state.) Function Option At reset Handling when unused
2
I/O
Identical to those for PA0 to PA3
No. 6278-8/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L Oscillator Circuit Options
Option Circuit Conditions and other notes
External clock
The OSC2 pin must be left open.
Two-pin RC oscillator
Ceramic oscillator
Ceramic oscillator element
Divider Circuit Options
Option Circuit Conditions and other notes * This option can be used with any of the three oscillator options. * The oscillator frequency or external clock frequency must not exceed 1444 kHz. (LC651154N, LC651152N) * The oscillator frequency or external clock frequency must not exceed 4330 kHz. (LC651154F, LC651152F) * The oscillator frequency or external clock frequency must not exceed 1040 kHz. (LC651154L, LC651152L)
Oscillator circuit
No divider
Oscillator circuit
Timing generator Divide-by-3 Timing generator Divide-by-4 Timing generator
Built-in divide-by-three circuit
* This option can only be used with the external clock and the ceramic oscillator options. * The oscillator frequency or external clock frequency must not exceed 4330 kHz.
Oscillator circuit
Built-in divide-by-four circuit
* This option can only be used with the external clock and the ceramic oscillator options. * The oscillator frequency or external clock frequency must not exceed 4330 kHz.
Caution: The following tables summarize the oscillator and divider circuit options. Use care when selecting these options.
No. 6278-9/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L Oscillator Options LC651154N, LC651152N
Circuit type Frequency 400 kHz Divider option (cycle time) 1/1 (10 s) 1/1 (5 s) 800 kHz Ceramic oscillator 1 MHz 1/3 (15 s) 1/4 (20 s) 1/1 (4 s) 1/3 (12 s) 1/4 (16 s) 4 MHz 200 k to 1444 kHz External clock used with the 2-pin RC oscillator circuit 600 k to 4330 kHz 800 k to 4330 kHz 1/3 (3 s) 1/4 (4 s) VDD range 3 to 6 V 3 to 6 V 3 to 6 V 3 to 6 V 3 to 6 V 3 to 6 V 3 to 6 V 3 to 6 V 3 to 6 V Cannot be used with the no divider circuit option. Notes Cannot be used with the divide-by-three and divide-by-four options.
1/1 (20 to 2.77 s) 3 to 6 V 1/3 (20 to 2.77 s) 3 to 6 V 1/4 (20 to 3.70 s) 3 to 6 V
Two-pin RC
Use the no divider circuit option and the 3 to 6 V recommended circuit constants. If using other circuit constants is unavoidable, the application must use a frequency identical to the external clock and observe the VDD range specification. External clock drive is not possible. To use external clock drive, select the 2-pin RC oscillator option.
External clock used with the ceramic oscillator option
LC651154F, LC651152F
Circuit type Ceramic oscillator External clock used with the 2-pin RC oscillator circuit External clock used with the ceramic oscillator option Frequency 4 MHz 200 k to 4330 kHz Divider option (cycle time) 1/1 (1 s) VDD range 2.5 to 6 V Notes
1/1 (20 to 0.92 s) 2.5 to 6 V
External clock drive is not possible. To use external clock drive, select the 2-pin RC oscillator option.
No. 6278-10/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L LC651154L, LC651152L
Circuit type Frequency 400 kHz Divider option (cycle time) 1/1 (10 s) 1/1 (5 s) 800 kHz Ceramic oscillator 1 MHz 1/3 (15 s) 1/4 (20 s) 1/1 (4 s) 1/3 (12 s) 1/4 (16 s) 4 MHz 200 k to 1040 kHz External clock used with the 2-pin RC oscillator circuit 600 k to 3120 kHz 800 k to 4160 kHz 1/4 (4 s) VDD range 2.2 to 6 V 2.2 to 6 V 2.2 to 6 V 2.2 to 6 V 2.2 to 6 V 2.2 to 6 V 2.2 to 6 V 2.2 to 6 V Cannot be used with either the no divider circuit option or the divide-by-three circuit option. Notes Cannot be used with the divide-by-three and divide-by-four options.
1/1 (20 to 3.84 s) 2.2 to 6 V 1/3 (20 to 3.84 s) 2.2 to 6 V 1/4 (20 to 3.84 s) 2.2 to 6 V
Two-pin RC
Use the no divider circuit option and the 2.2 to 6 V recommended circuit constants. If using other circuit constants is unavoidable, the application must use a frequency identical to the external clock and observe the VDD range specification. External clock drive is not possible. To use external clock drive, select the 2-pin RC oscillator option.
External clock used with the ceramic oscillator option
Port C and D Output Level During Reset Option The output level during a reset can be selected from the two options below in 4-bit units for the C and D ports.
Option High-level output during reset Low-level output during reset Conditions and other notes Ports C and D in 4-bit units Ports C and D in 4-bit units
Port Output Type Option The following two options may be selected for the I/O ports individually (bit units).
Option Circuit Applicable ports
1. Open-drain output
Ports A, C, D, E, F, and G
2. Built-in pull-up resistor
Watchdog Reset Option This option allows the PE1/WDR pin to be selected either to be used as the normal port PE1 or to be used as the watchdog reset pin WDR.
No. 6278-11/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L LC651154N, 651152N Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Output voltage Input voltage
Symbol VDD max VO VI (1) VI (2) VIO (1)
Conditions
Applicable pins and notes VDD OSC2 OSC1 *1 TEST, RES, AV+, AV-
Ratings -0.3 to +7.0 Allowed up to the generated voltage. -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +15 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -2 to +20 -2 to +20
Unit
V
PC0 to 3, PD0 to 3, PE0, 1, PF0 to 3 PC0 to 3, PD0 to 3, PE0, 1, PF0 to 3 PC0 to 3, PG0 to 3
Open-drain specification ports Pull-up resistor specification ports
I/O voltage
VIO (2) VIO (3) IOP IOA IOA (1)
Peak output current
I/O ports Per single pin, averaged over 100 ms The total current for PC0 to PC3, PD0 to PD3, and PE0 to PE1 *2 I/O ports PC0 to 3 PD0 to 3 PE0 to 1
-15 to +100
Average output current IOA (2)
mA
PF0 to 3 The total current for PF0 to PF3, PG0 to 3 PG0 to PG3, and PA0 to PA3 (See note 2.) *2 PA0 to 3
-15 to +100
Pd max (1) Ta = -40 to +85C (DIP package) Allowable power dissipation Pd max (2) Ta = -40 to +85C (MFP package) Pd max (3) Ta = -40 to +85C (SSOP package) Operating temperature Storage temperature Topr Tstg
310 220 160 -40 to +85 -55 to +125 C mW
Allowable Operating Ranges at Ta = -40 to +85C, VSS = 0 V, VDD = 3.0 to 6.0 V (Unless otherwise specified.)
Parameter Operating supply voltage Standby supply voltage Symbol VDD VST VIH (1) VIH (2) VIH (3) High-level input voltage VIH (4) Conditions Applicable pins and notes VDD RAM and register values retained*3 VDD Output n-channel transistors off Output n-channel transistors off Output n-channel transistors off Output n-channel transistors off Ports C, D, E, and F with open-drain specifications Ports C, D, E, and F with pull-up resistor specifications Port A, G The INT, SCK, and SI pins with open-drain specifications The INT, SCK, and SI pins with pull-up resistor specifications RES OSC1 Ratings min 3.0 1.8 0.7 VDD 0.7 VDD 0.7 VDD 0.8 VDD typ max 6.0 6.0 13.5 VDD VDD 13.5 V Unit
VIH (5) VIH (6) VIH (7)
Output n-channel transistors off VDD = 1.8 to 6.0 V External clock specifications
0.8 VDD 0.8 VDD 0.8 VDD
VDD VDD VDD
Continued on next page.
No. 6278-12/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Continued from preceding page.
Parameter Symbol VIL (1) VIL (2) VIL (3) VIL (4) Low-level input voltage VIL (5) VIL (6) VIL (7) VIL (8) VIL (9) VIL (10) Conditions Output n-channel transistors off VDD = 4 to 6 V Output n-channel transistors off VDD = 3 to 6 V Output n-channel transistors off VDD = 4 to 6 V Output n-channel transistors off VDD = 3 to 6 V External clock specifications VDD = 4 to 6 V External clock specifications VDD = 3 to 6 V VDD = 4 to 6 V VDD = 3 to 6 V VDD = 4 to 6 V VDD = 3 to 6 V The clock may have a frequency up to 4.33 MHz when either the divide-byVDD = 3 to 6 V three or divide-by-four internal divider circuit option is used. Figure 1. text Either the divide-bythree or divide-by-four internal divider circuit must be used if the clock frequency exceeds 1.444 MHz. VDD = 3 to 6 V OSC1 200 4330 kHz Applicable pins and notes Port Port INT, SCK, SI INT, SCK, SI OSC1 OSC1 TEST TEST RES RES Ratings min VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS typ max 0.3 VDD 0.25 VDD 0.25 VDD 0.2 VDD 0.25 VDD 0.2 VDD 0.3 VDD 0.25 VDD 0.25 VDD 0.2 VDD V Unit
Operating frequency (cycle time)
fop (Tcyc)
200 (20)
1444 kHz (s) (2.77)
External clock conditions Frequency
Pulse width Rise and fall times Recommended oscillator circuit constants
textH, textL textR, textF
VDD = 3 to 6 V VDD = 3 to 6 V
OSC1 OSC1
69 ns 50
Cext Rext
Figure 2
VDD = 3 to 6 V
OSC1, OSC2
270 5% 12 1%
pF k
Two-pin RC oscillator Cext Rext Ceramic oscillator *4 Figure 3 Figure 2 VDD = 3 to 6 V OSC1, OSC2 270 5% 5.6 1% See table 1. pF k
No. 6278-13/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L Electrical Characteristics at Ta = -40 to +85C, VSS = 0 V, VDD = 3.0 to 6.0 V (Unless otherwise specified.)
Parameter Symbol Conditions * Output n-channel transistors off (Including the n-channel transistor off leakage current.) * VIN = 13.5 V Applicable pins and notes Ports C, D, E and F with the open-drain specifications Ratings min typ max Unit
IIH (1)
5.0
High-level input current IIH (2)
* Output n-channel transistors off (Including the n-channel transistor Ports A and G with the off leakage current.) open-drain specifications * VIN = VDD When an external clock is used, VIN = VDD * Output n-channel transistors off * VIN = VSS * Output n-channel transistors off * VIN = VSS VIN = VSS When an external clock is used, VIN = VSS * IOH = -50 A * VDD = 4.0 to 6.0 V IOH = -10 A * IOL = 10 mA * VDD = 4.0 to 6.0 V When IOL = 1 mA and the IOL for each port is 1 mA or less. OSC1 Ports with the open-drain specifications Ports with the pull-up resistor specifications RES OSC1 Ports with the pull-up resistor specifications Ports with the pull-up resistor specifications Port Port 0.1 VDD RES, INT, SCK, SI, and OSC1 with Schmitt specifications*5 0.4 VDD 0.2 VDD -1.0 -1.3 -45 -1.0 -0.35 -10
1.0
A
IIH (3) IIL (1) Low-level input current IIL (2) IIL (3) IIL (4) VOH (1) High-level output voltage VOH (2) VOL (1) Low-level output voltage VOL (2) Schmitt characteristics Hysteresis voltage High-level threshold voltage Low-level threshold voltage VHIS VtH VtL
1.0
mA
A
VDD - 1.2 VDD - 0.5 1.5 0.5 V
0.8 VDD 0.6 VDD
Current drain *6 Two-pin RC oscillator Ceramic oscillator
* Operating, with the output n-channel transistors off IDDOP (1) * With the ports at VDD * Figure 2, fosc = 800 kHz (typical)
VDD
1.5
4
IDDOP (2) * Figure 3, 4 MHz, divide-by-three circuit used VDD IDDOP (3) * Figure 3, 4 MHz, divide-by-four circuit used VDD IDDOP (4) * Figure 3, 400 kHz IDDOP (5) * Figure 3, 800 kHz * 200 kHz to 1444 kHz, no divider circuit * 600 kHz to 4330 kHz, divide-byIDDOP (6) three circuit used * 800 kHz to 4330 kHz, divide-byfour circuit used Output n-channel transistors off, VDD = 6 V Ports at VDD, VDD = 3 V VDD VDD
1.5 1.5 1.0 1.5
5 4 2.5 4 mA
External clock
VDD
1.5
5
VDD VDD
0.05 0.025
10 A 5
Standby mode
IDDst
Continued on next page.
No. 6278-14/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Continued from preceding page.
Parameter Oscillator characteristics Ceramic oscillator Oscillator frequency fCFOSC*7 Symbol Conditions * Figure 3, fo = 400 kHz * Figure 3, fo = 800 kHz * Figure 3, fo = 1 MHz * Figure 3, fo = 4 MHz, with the divide-by-three or divide-by-four circuit used. * Figure 4, fo = 400 kHz * Figure 4, fo = 800 kHz, 1 MHz, or 4 MHz, with the divide-by-three or divide-by-four circuit used. * Figure 2, Cext = 270 pF 5% * Figure 2, Rext = 5.6 k 1% * Figure 2, Cext = 270 pF 5% * Figure 2, Rext = 12 k 1% * Output n-channel transistors off * VIN = VSS, VDD = 5 V VIN = VSS, VDD = 5 V OSC1, OSC2 OSC1, OSC2 Pull-up resistor specification ports RES 587 290 8 200 800 400 14 500 See figure 5. * f = 1 MHz * With all pins other than the pin being tested at VIN = VSS. Figure 6 Figure 6 Figure 6 Figure 6 Figure 6 Figure 6 * Stipulated with respect to the rising edge of SCK. * Figure 6 SCK SCK SCK SCK SCK SCK 1.0 32 x TCYC s tICK SI 0.4 1.0 32 x TCYC 2.0 64 x TCYC*9 Applicable pins and notes OSC1, OSC2 OSC1, OSC2 OSC1, OSC2 OSC1, OSC2 Ratings min 392 784 980 3920 typ 400 800 1000 4000 max 408 816 1020 4080 Unit
kHz
Oscillator stabilization time (note 8)
tCFS
10 10
ms
Two-pin RC oscillator Oscillator frequency
1298 kHz 818 30 800
fMOSC
Pull-up resistor I/O ports RES External reset characteristics Reset time Pin capacitances Serial clock Input clock cycle time Output clock cycle time Input clock low-level pulse width Output clock low-level pulse width Input clock high-level pulse width Output clock high-level pulse width Serial input Data setup time
RPP Ru tRST
k
Cp
10
pF
tCKCY (1) tCKCY (2) tCKL (1) tCKL (2) tCKH (1) tCKH (2)
Data hold time Serial output
tCKI
SI * Stipulated with respect to the falling edge of SCK. * With an external resistor of 1 k and an external capacitor of 50 pF SO on only the n-channel open-drain pins. * Figure 6
0.4
Output delay time
tCKO
0.6
Continued on next page.
No. 6278-15/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Continued from preceding page.
Parameter Pulse output function Period tPCY Symbol Conditions * Figure 7 * TCYC = 4 x system clock period * With an external resistor of 1 k and an external capacitor of 50 pF on only the n-channel open-drain pins. Applicable pins and notes Ratings min typ 64 x TCYC 32 x TCYC 10% 32 x TCYC 10% 8 AV+ = VDD AV- = VSS When the A/D converter speed is normal (1:1), namely 26 x TCYC When the A/D converter speed is one half (1:2), namely 51 x TCYC AV+ VDD = 3 to 6 V AV+ = VDD, AV- = VSS AV- AV+, AV- AD0 to AD7 Including the output off leakage current. VAIN = VDD Analog port input current IAIN VAIN = VSS When PE1 has the open-drain specifications. When PE1 has the open-drain specifications. When PE1 has the open-drain specifications. Figure 8 Figure 8 When PE1 has the open-drain specifications. When PE1 has the open-drain specifications. When PE1 has the open-drain specifications. Figure 8 Figure 8 VDD = 3 to 6 V WDR WDR WDR 40 18 100 1% VDD = 3 to 6 V WDR WDR WDR WDR WDR 100 36 0.047 5% 680 1% 100 1% AD0 to AD7 (The I/O shared function ports have opendrain specifications.) WDR WDR 72 (TCYC = 2.77 s) 141 (TCYC = 2.77 s) AV- VSS 200 AV- 500 1 2 312 (TCYC = 12 s) 612 (TCYC = 12 s) VDD AV+ 800 AV+ 1 bit LSB max Unit
PE0
High-level pulse width
tPH
PE0
s
Low-level pulse width Resolution Absolute precision
tPL
PE0
A/D converter characteristics
Conversion time
TCAD
s
Input reference voltage Input reference current range Analog input voltage range
AV+ AV- IRIF VAIN
V A V
A -1
Cw Recommended constants*10 Rw RI Watchdog timer Clear time (discharge) Clear period (charge) tWCT tWCCY Cw Recommended constants*10 Rw RI Clear time (discharge) Clear period (charge) tWCT tWCCY
0.1 5% 680 1%
F k s ms F k s ms
Notes:1. Allowed up to the amplitude generated when the oscillator shown in figure 3 is used with the recommended circuit constants and driven by the IC. 2. The average over a 100 ms period. 3. The operating VDD supply voltage must be maintained from the point the HALT instruction is executed until the IC has fully entered the standby state. Applications must also assure that no chattering occurs on the PA3 pin during the HALT instruction execution cycle. 4. Recommended circuit constants that have been verified to oscillate stably according to the oscillator element manufacturer using the Sanyostipulated oscillator characteristics evaluation board. 5. The OSC1 pin will have Schmitt characteristics when external clock oscillator is selected with the two-pin RC oscillator option. 6. These are the results of testing using our (Sanyo's) characteristics evaluation board with the recommended circuit constants used as external components. The current flowing in the IC's output transistors and transistors that have pull-up resistors is not included. 7. fCFOSC is the frequency when the recommended circuit constants from table 1 are used as external components. 8. Indicates the time required to achieve stable oscillation from the point VDD rises above the lower limit of the operating voltage range. 9. TCYC = 4 x the system clock period 10. If the application could be used in an environment in which condensation is possible, extra care with respect to the leakage between PE1 and adjacent pins and leakage associated with external resistors and capacitor is required during design.
No. 6278-16/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
External clock
open
Figure 1 External Clock Input Waveform
Ceramic oscillator element
Figure 2 Two-Pin RC Oscillator Circuit
Figure 3 Ceramic Oscillator Circuit
No. 6278-17/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Lower limit for the operating supply voltage
Stable oscillation Oscillation stabilization time tCFS
Figure 4 Oscillation Stabilization Time
Table 1 Recommended Ceramic Oscillator Circuit Constants
4 MHz (Murata Mfg. Co., Ltd.) CSA4.00MG CST4.00MGW (Internal capacitor) 4 MHz (Kyocera Corporation) KBR4.0MSA KBR4.0MKS (Internal capacitor) 1 MHz (Murata Mfg. Co., Ltd.) CSB1000J C1 C2 R C1 C2 R C1 C2 R 800 kHz (Murata Mfg. Co., Ltd.) CSB800J C1 C2 R 400 kHz (Murata Mfg. Co., Ltd.) CSB400P C1 C2 R 33 pF 10% 33 pF 10% 0 33 pF 10% 33 pF 10% 0 100 pF 10% 100 pF 10% 3.3 k 100 pF 10% 100 pF 10% 3.3 k 220 pF 10% 220 pF 10% 3.3 k Note: If the power supply rise time is zero, the reset time when CRES = 0.1 F will be between 10 and 100 ms. If the power supply rise time is long, increase the value of CRES so that the reset time is at least 10 ms.
Figure 5 Reset Circuit
No. 6278-18/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Input data
Load circuit
Output data
Figure 6 Serial I/O Timing
The load conditions are the same as those in figure 5.
Figure 7 Port PE0 Pulse Output Timing
tWCCY: tWCT:
The charge time due to the time constant of the circuit consisting of the external components Cw, Rw, and Rl. The discharge time due to software processing.
Figure 8 Watchdog Timer Waveform
No. 6278-19/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L RC Oscillator Characteristics for the LC651154N and LC651152N Figure 9 shows the RC oscillator characteristics for the LC651154N and LC651152N. However, the sample-to-sample variation in the LC651154N and LC651152N RC oscillator frequency described below does occur. 1) When: VDD = 3.0 to 6.0 V, Ta = -40 to +85C External constants: Cext = 270 pF Rext = 12.0 k fMOSC will be: 290 kHz fMOSC 818 kHz 2) When: VDD = 3.0 to 6.0 V, Ta = -40 to +85C External constants: Cext = 270 pF Rext = 5.6 k fMOSC will be: 587 kHz fMOSC 1298 kHz Therefore, only the above circuit constants are recommended. If use of circuit constants other than the above is unavoidable, they must be in the following ranges. Cext = 150 to 390 pF Rext = 3 to 20 k (See figure 9.) Notes * The oscillator frequency must be in the range 350 to 850 kHz when VDD = 5.0 V and Ta = 25C. * Applications must be designed to have adequate margins so that the oscillator frequency falls in the operating clock frequency range (see the oscillator divider option table) for the voltage range VDD = 3.0 to 6.0 V and for the temperature range Ta = -40 to +85C.
These characteristics curves are for reference purposes only and are not guaranteed.
Figure 9 RC Oscillator Frequency Data (Representative Values)
No. 6278-20/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L LC651154F, 651152F Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Output voltage Input voltage Symbol VDD max VO VI (1) VI (2) VIO (1) I/O voltage VIO (2) VIO (3) Peak output current IOP IOA IOA (1) Average output current IOA (2) Per single pin, averaged over 100 ms The total current for PC0 to PC3, PD0 to PD3, and PE0 and PE1 *2 Conditions Applicable pins and notes VDD OSC2 OSC1 *1 TEST, RES, AV+, AV- PC0 to PC3, PD0 to PD3, PE0, 1, PF0 to PF3 Open-drain specification ports PC0 to PC3, PD0 to PD3, PE0, 1, PF0 to PF3 Pull-up resistor specification ports PA0 to PA3, PG0 to PG3 I/O ports I/O ports PC0 to PC3 PD0 to PD3 PE0 and PE1 -15 to +100 mA Ratings -0.3 to +7.0 Allowed up to the generated voltage. -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +15 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -2 to +20 -2 to +20 V Unit
PF0 to PF3 The total current for PF0 to PF3, PG0 to PG3, PG0 to PG3 and PA0 to PA3 (See note 2.) *2 PA0 to PA3
-15 to +100
Pd max (1) Ta = -40 to +85C (DIP package) Allowable power dissipation Pd max (2) Ta = -40 to +85C (MFP package) Pd max (3) Ta = -40 to +85C (SSOP package) Operating temperature Storage temperature Topr Tstg
310 220 160 -40 to +85 -55 to +125 C mW
Allowable Operating Ranges at Ta = -40 to +85C, VSS = 0 V, VDD = 2.5 to 6.0 V (Unless otherwise specified.)
Parameter Operating supply voltage Standby supply voltage Symbol VDD VST VIH (1) VIH (2) VIH (3) High-level input voltage VIH (4) Conditions Applicable pins and notes VDD RAM and register values retained*3 VDD Output n-channel transistors off Output n-channel transistors off Output n-channel transistors off Output n-channel transistors off Ports C, D, E, and F with open-drain specifications Ports C, D, E, and F with pull-up resistor specifications Port A, G The INT, SCK, and SI pins with open-drain specifications The INT, SCK, and SI pins with pull-up resistor specifications RES OSC1 Ratings min 2.5 1.8 0.7 VDD 0.7 VDD 0.7 VDD 0.8 VDD typ max 6.0 6.0 13.5 VDD VDD 13.5 V Unit
VIH (5) VIH (6) VIH (7)
Output n-channel transistors off VDD = 1.8 to 6.0 V External clock specifications
0.8 VDD 0.8 VDD 0.8 VDD
VDD VDD VDD
Continued on next page.
No. 6278-21/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Continued from preceding page.
Parameter Symbol VIL (1) VIL (2) VIL (3) VIL (4) Low-level input voltage VIL (5) VIL (6) VIL (7) VIL (8) VIL (9) VIL (10) Operating frequency (cycle time) External clock conditions Frequency Pulse width Rise and fall times Recommended oscillator circuit constants Ceramic oscillator *4 text textH, textL Figure 1. textR, textF Figure 2 OSC1 OSC1 OSC1 See table 1. 200 69 50 4330 kHz ns ns fop (Tcyc) Conditions Output n-channel transistors off VDD = 4 to 6 V Output n-channel transistors off VDD = 4 to 6 V External clock specifications VDD = 4 to 6 V VDD = 4 to 6 V VDD = 4 to 6 V Applicable pins and notes Port Ratings min VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 200 (20) typ max 0.3 VDD 0.2 VDD 0.25 VDD 0.15 VDD 0.25 VDD 0.15 VDD 0.3 VDD 0.2 VDD 0.25 VDD 0.15 VDD 4330 kHz (s) (0.92) V Unit
Output n-channel transistors off VDD = 2.5 to 6 V Port INT, SCK, SI Output n-channel transistors off VDD = 2.5 to 6 V INT, SCK, SI OSC1 External clock specifications VDD = 2.5 to 6 V OSC1 TEST VDD = 2.5 to 6 V TEST RES VDD = 2.5 to 6 V RES
Electrical Characteristics at Ta = -40 to +85C, VSS = 0 V, VDD = 2.5 to 6.0 V (Unless otherwise specified.)
Parameter Symbol Conditions Applicable pins and notes Ratings min typ max Unit
IIH (1)
* Output n-channel transistors off Ports C, D, E and F with (Including the n-channel transistor the open-drain off leakage current.) specifications * VIN = 13.5 V * Output n-channel transistors off (Including the n-channel transistor Ports A and G with the off leakage current.) open-drain specifications * VIN = VDD When an external clock is used, VIN = VDD * Output n-channel transistors off * VIN = VSS * Output n-channel transistors off * VIN = VSS VIN = VSS When an external clock is used, VIN = VSS * IOH = -50 A * VDD = 4.0 to 6.0 V IOH = -10 A * IOL = 10 mA * VDD = 4.0 to 6.0 V When IOL = 1 mA and the IOL for each port is 1 mA or less. OSC1 Ports with the open-drain specifications Ports with the pull-up resistor specifications RES OSC1 Ports with the pull-up resistor specifications Ports with the pull-up resistor specifications Port Port 0.1 VDD RES, INT, SCK, SI, and OSC1 with Schmitt specifications*5 0.4 VDD 0.25 VDD -1.0 -1.3 -45 -1.0 VDD - 1.2 VDD - 0.5 -0.35 -10
5.0
High-level input current IIH (2) IIH (3)
1.0
A
1.0
IIL (1) Low-level input current IIL (2) IIL (3) IIL (4) VOH (1) High-level output voltage VOH (2) VOL (1) Low-level output voltage VOL (2) Schmitt characteristics Hysteresis voltage High-level threshold voltage Low-level threshold voltage VHIS VtH VtL
mA
A
1.5 0.5 V
0.8 VDD 0.6 VDD
Continued on next page.
No. 6278-22/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Continued from preceding page.
Parameter Current drain*6 IDDOP (1) * Figure 2, 4 MHz * 200 kHz to 4330 kHz Ceramic oscillator * Operating, with the output IDDOP (2) n-channel transistors off and the ports at VDD. IDDst * Output n-channel transistors off VDD = 6 V * Ports at VDD, VDD = 2.5 V * Figure 2, fo = 4 MHz * Figure 3, fo = 4 MHz * Output n-channel transistors off * VIN = VSS, VDD = 5 V VIN = VSS, VDD = 5 V Pull-up resistor specification ports RES 8 200 14 500 See figure 4. * f = 1 MHz * With all pins other than the pin being tested at VIN = VSS. Figure 5 Figure 5 Figure 5 Figure 5 Figure 5 Figure 5 SCK SCK SCK SCK SCK SCK 0.6 32 x TCYC 0.6 32 x TCYC 2.0 64 x TCYC*9 VDD 2 6 mA VDD VDD VDD OSC1, OSC2 3920 2 0.05 0.025 4000 6 10 5 4080 10 30 800 kHz ms k Symbol Conditions Applicable pins and notes Ratings min typ max Unit
Standby mode Oscillator characteristics Ceramic oscillator Oscillator frequency*8 Pull-up resistor I/O ports RES External reset characteristics Reset time Pin capacitances Serial clock Input clock cycle time Output clock cycle time Input clock low-level pulse width Output clock low-level pulse width Input clock high-level pulse width Output clock high-level pulse width Serial input Data setup time
A
fCFOSC*7 tCFS RPP Ru tRST Cp
10
pF
tCKCY (1) tCKCY (2) tCKL (1) tCKL (2) tCKH (1) tCKH (2)
tICK
* Stipulated with respect to the rising edge of SCK. * Figure 5
SI
0.2 s
Data hold time Serial output
tCKI
SI * Stipulated with respect to the falling edge of SCK. * With an external resistor of 1 k SO and an external capacitor of 50 pF on only the n-channel open-drain pins. * Figure 5 * Figure 6 * TCYC = 4 x system clock period * With an external resistor of 1 k and an external capacitor of 50 pF on only the n-channel open-drain pins. PE0
0.2
Output delay time
tCKO
0.4
Pulse output function Period
tPCY
64 x TCYC 32 x TCYC 10% 32 x TCYC 10%
High-level pulse width
tPH
PE0
Low-level pulse width
tPL
PE0
Continued on next page.
No. 6278-23/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Continued from preceding page.
Parameter Resolution Absolute precision AV+ = VDD A/D converter speed 1/1 When the A/D converter speed is normal (1/1), namely 26 x TCYC When the A/D converter speed is one half (1/2), namely 51 x TCYC Symbol Conditions VDD = 3 to 6 V VDD = 3.5 to 6 V 24 (TCYC = 0.92 s) 47 (TCYC = 0.92 s) AV+ AV- AV+ = VDD, AV- = VSS AV+, AV- AD0 to AD7 Including the output off leakage current. VAIN = VDD Analog port input current IAIN VAIN = VSS When PE1 has the open drain specifications. When PE1 has the open drain specifications. When PE1 has the open drain specifications. Figure 7 Figure 7 VDD = 3 to 6 V AD0 to AD7 (The I/O shared function ports have opendrain specifications.) WDR WDR WDR WDR WDR 10 4.2 AV- VSS 200 AV- 500 AV- = VSS A/D converter speed 1/2 VDD = 3.5 to 6 V VDD = 3.5 to 6 V Applicable pins and notes Ratings min typ 8 1 1 2 2 312 (TCYC = 12 s) 612 (TCYC = 12 s) VDD AV+ 800 AV+ 1 A -1 s max Unit bit LSB
A/D converter characteristics
Conversion time
TCAD
VDD = 3 to 6 V
Input reference voltage Input reference current range Analog input voltage range
AV+ AV- IRIF VAIN
V A V
Cw Watchdog timer Recommended constants*10 Rw RI Clear time (discharge) Clear period (charge) tWCT tWCCY
0.01 5% 680 1% 100 1%
F k s ms
Notes:1. Allowed up to the amplitude generated when the oscillator shown in figure 2 is used with the recommended circuit constants and driven by the IC. 2. The average over a 100 ms period. 3. The operating VDD supply voltage must be maintained from the point the HALT instruction is executed until the IC has fully entered the standby state. Applications must also assure that no chattering occurs on the PA3 pin during the HALT instruction execution cycle. 4. Recommended circuit constants that have been verified to oscillate stably according to the oscillator element manufacturer using the Sanyostipulated oscillator characteristics evaluation board. 5. The OSC1 pin will have Schmitt characteristics when external clock oscillator is selected with the two-pin RC oscillator option. 6. These are the results of testing using our (Sanyo's) characteristics evaluation board with the recommended circuit constants used as external components. The current flowing in the IC's output transistors and transistors that have pull-up resistors is not included. 7. fCFOSC is the frequency when the recommended circuit constants from table 1 are used as external components. 8. Indicates the time required to achieve stable oscillation from the point VDD rises above the lower limit of the operating voltage range (See figure 3). 9. TCYC = 4 x the system clock period 10. If the application could be used in an environment in which condensation is possible, extra care with respect to the leakage between PE1 and adjacent pins and leakage associated with external resistors and capacitor is required during design.
No. 6278-24/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
External clock
open
Figure 1 External Clock Input Waveform
Ceramic oscillator element
Figure 2 Ceramic Oscillator Circuit
No. 6278-25/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Lower limit for the operating supply voltage
Stable oscillation Oscillation stabilization time tCFS
Figure 4 Oscillation Stabilization Time
Table 1 Recommended Ceramic Oscillator Circuit Constants
4 MHz (Murata Mfg. Co., Ltd.) CSA4.00MG CST4.00MGW (Internal capacitor) 4 MHz (Kyocera Corporation) KBR4.0MSA KBR4.0MKS (Internal capacitor) C1 C2 R C1 C2 R 33 pF 10% 33 pF 10% 0 33 pF 10% 33 pF 10% 0
Figure 5 Reset Circuit
Note: If the power supply rise time is zero, the reset time when CRES = 0.1 F will be between 10 and 100 ms. If the power supply rise time is long, increase the value of CRES so that the reset time is at least 10 ms.
No. 6278-26/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Input data
Load circuit
Output data
Figure 5 Serial I/O Timing
The load conditions are the same as those in figure 4.
Figure 6 Port PE0 Pulse Output Timing
tWCCY: tWCT:
The charge time due to the time constant of the circuit consisting of the external components Cw, Rw, and Rl. The discharge time due to software processing.
Figure 7 Watchdog Timer Waveform
No. 6278-27/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L LC651154L, 651152L Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Output voltage Input voltage Symbol VDD max VO VI (1) VI (2) VIO (1) I/O voltage VIO (2) VIO (3) Peak output current IOP IOA IOA (1) Average output current IOA (2) Per single pin, averaged over 100 ms The total current for PC0 to PC3, PD0 to PD3, and PE0 to PE1 *2 Conditions Applicable pins and notes VDD OSC2 OSC1 *1 TEST, RES, AV+, AV- PC0 to PC3, PD0 to PD3, PE0, 1, PF0 to PF3 Open-drain specification ports PC0 to PC3, PD0 to PD3, PE0, 1, PF0 to PF3 Pull-up resistor specification ports PA0 to PA3, PG0 to PG3 I/O ports I/O ports PC0 to PC3 PD0 to PD3 PE0 to PE1 -15 to +100 mA Ratings -0.3 to +7.0 Allowed up to the generated voltage. -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -0.3 to +15 -0.3 to VDD + 0.3 -0.3 VDD + 0.3 -2 to +20 -2 to +20 V Unit
PF0 to PF3 The total current for PF0 to PF3, PG0 to PG3, PG0 to PG3 and PA0 to PA3 (See note 2.) *2 PA0 to PA3
-15 to +100
Pd max (1) Ta = -40 to +85C (DIP package) Allowable power dissipation Pd max (2) Ta = -40 to +85C (MFP package) Pd max (3) Ta = -40 to +85C (SSOP package) Operating temperature Storage temperature Topr Tstg
310 220 160 -40 to +85 -55 to +125 C mW
Allowable Operating Ranges at Ta = -40 to +85C, VSS = 0 V, VDD = 2.2 to 6.0 V (Unless otherwise specified.)
Parameter Operating supply voltage Standby supply voltage Symbol VDD VST VIH (1) VIH (2) VIH (3) High-level input voltage VIH (4) Conditions Applicable pins and notes VDD RAM and register values retained*3 VDD Output n-channel transistors off Output n-channel transistors off Output n-channel transistors off Output n-channel transistors off Ports C, D, E, and F with open-drain specifications Ports C, D, E, and F with pull-up resistor specifications Port A, G The INT, SCK, and SI pins with open-drain specifications The INT, SCK, and SI pins with pull-up resistor specifications RES OSC1 Port INT, SCK, SI OSC1 TEST RES Ratings min 2.2 1.8 0.7 VDD 0.7 VDD 0.7 VDD 0.8 VDD typ max 6.0 6.0 13.5 VDD VDD 13.5 V 0.8 VDD 0.8 VDD 0.8 VDD VSS VSS VSS VSS VSS VDD VDD VDD 0.2 VDD 0.15 VDD 0.15 VDD 0.2 VDD 0.15 VDD Unit
VIH (5) VIH (6) VIH (7) VIL (1) VIL (2) Low-level input voltage VIL (3) VIL (4) VIL (5)
Output n-channel transistors off VDD = 1.8 to 6.0 V External clock specifications Output n-channel transistors off Output n-channel transistors off Output n-channel transistors off
Continued on next page.
No. 6278-28/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Continued from preceding page.
Parameter Operating frequency (cycle time) External clock conditions Frequency Pulse width Rise and fall times Recommended oscillator circuit constants Two-pin RC oscillator Ceramic oscillator *4 Cext Rext Figure 3 Figure 2 OSC1, OSC2 270 5% 12 1% See table 1. pF k text textH, textL textR, textF Symbol Conditions The clock may have a frequency up to 4.16 MHz when the divide-by-four internal divider circuit option is used. Figure 1. OSC1 Either the divide-by-three or divide-byfour internal divider circuit must be used if OSC1 the clock frequency exceeds 1.040 MHz. OSC1 200 100 100 4160 kHz ns ns Applicable pins and notes Ratings min 200 (20) typ max Unit
fop (Tcyc)
1040 kHz (s) (3.84)
No. 6278-29/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L Electrical Characteristics at Ta = -40 to +85C, VSS = 0 V, VDD = 2.2 to 6.0 V (Unless otherwise specified.)
Parameter Symbol Conditions Applicable pins and notes Ratings min typ max Unit
IIH (1)
* Output n-channel transistors off Ports C, D, E and F with (Including the n-channel transistor the open-drain off leakage current.) specifications * VIN = 13.5 V * Output n-channel transistors off (Including the n-channel transistor Ports A and G with the off leakage current.) open-drain specifications * VIN = VDD When an external clock is used, VIN = VDD * Output n-channel transistors off * VIN = VSS * Output n-channel transistors off * VIN = VSS VIN = VSS When an external clock is used, VIN = VSS * IOH = -10 A * IOL = 3 mA When IOL = 1 mA and the IOL for each port is 1 mA or less. OSC1 Ports with the open-drain specifications Ports with the pull-up resistor specifications RES OSC1 Ports with the pull-up resistor specifications Port Port 0.1 VDD RES, INT, SCK, SI, and OSC1 with Schmitt specifications*5 0.4 VDD 0.2 VDD * Operating, with the output n-channel transistors off * With the ports at VDD * Figure 2, fosc = 800 kHz (typical) -1.0 -1.3 -45 -1.0 -0.35 -10
5.0
High-level input current IIH (2) IIH (3)
1.0
A
1.0
IIL (1) Low-level input current IIL (2) IIL (3) IIL (4) High-level output voltage VOH VOL (1) Low-level output voltage VOL (2) Schmitt characteristics Hysteresis voltage High-level threshold voltage Low-level threshold voltage *6 IDDOP (1) VHIS VtH VtL
mA A
VDD - 0.5 1.5 0.4 V
0.8 VDD 0.6 VDD
Current drain
Two-pin RC oscillator
VDD
1.0
4
Ceramic oscillator
IDDOP (2) * Figure 3, 4 MHz, divide-by-four circuit used VDD * Figure 3, 4 MHz, divide-by-four circuit used VDD IDDOP (3) VDD = 2.2 V IDDOP (4) * Figure 3, 400 kHz IDDOP (5) * Figure 3, 800 kHz * 200 kHz to 1024 kHz, no divider circuit * 600 kHz to 3120 kHz, divide-byIDDOP (6) three circuit used * 800 kHz to 4160 kHz, divide-byfour circuit used IDDst Output n-channel transistors off, VDD = 6 V Ports at VDD, VDD = 2.2 V VDD VDD
1.5 0.5 1.0 1.5
4 1 2.5 4 mA
External clock
VDD
1.5
4
VDD VDD
0.05 0.020
10 A 4
Standby mode
Continued on next page.
No. 6278-30/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Continued from preceding page.
Parameter Oscillator characteristics Ceramic oscillator Oscillator frequency fCFOSC*7 Symbol Conditions * Figure 3, fo = 400 kHz * Figure 3, fo = 800 kHz * Figure 3, fo = 1 MHz * Figure 3, fo = 4 MHz, with the divide-by-four circuit used. * Figure 4, fo = 400 kHz * Figure 4, fo = 800 kHz, 1 MHz, or 4 MHz, with the divide-by-four circuit used. * Figure 2, Cext = 270 pF 5% * Figure 2, Rext = 5.6 k 1% * Output n-channel transistors off * VIN = VSS, VDD = 5 V VIN = VSS, VDD = 5 V OSC1, OSC2 Pull-up resistor specification ports RES 290 8 200 400 14 500 See figure 5. * f = 1 MHz * With all pins other than the pin being tested at VIN = VSS. Figure 6 Figure 6 Figure 6 Figure 6 Figure 6 Figure 6 SCK SCK SCK SCK SCK SCK 2.0 32 x TCYC 2.0 32 x TCYC 2.0 64 x TCYC*9 Applicable pins and notes OSC1, OSC2 OSC1, OSC2 OSC1, OSC2 OSC1, OSC2 Ratings min 392 784 980 3920 typ 400 800 1000 4000 max 408 816 1020 4080 Unit
kHz
Oscillator stabilization time *8
tCFS
10 10
ms
Two-pin RC oscillator Oscillator frequency Pull-up resistor I/O ports RES External reset characteristics Reset time Pin capacitances Serial clock Input clock cycle time Output clock cycle time Input clock low-level pulse width Output clock low-level pulse width Input clock high-level pulse width Output clock high-level pulse width Serial input Data setup time
fMOSC RPP Ru tRST
841 30 800
kHz
k
Cp
10
pF
tCKCY (1) tCKCY (2) tCKL (1) tCKL (2) tCKH (1) tCKH (2)
tICK
* Stipulated with respect to the rising edge of SCK. * Figure 6
SI
0.5
s
Data hold time Serial output
tCKI
SI * Stipulated with respect to the falling edge of SCK. * With an external resistor of 1 k SO and an external capacitor of 50 pF on only the n-channel open-drain pins. * Figure 6 * Figure 7 * TCYC = 4 x system clock period * With an external resistor of 1 k and an external capacitor of 50 pF on only the n-channel open-drain pins.
0.5
Output delay time
tCKO
1.0
Pulse output function Period tPCY
PE0
64 x TCYC
High-level pulse width
tPH
PE0
32 x TCYC 10% 32 x TCYC 10%
Low-level pulse width
tPL
PE0
Continued on next page.
No. 6278-31/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Continued from preceding page.
Parameter Resolution Absolute precision AV+ = VDD AV- = VSS When the A/D converter speed is normal (1/1), namely 26 x TCYC When the A/D converter speed is one half (1/2), namely 51 x TCYC AV+ VDD = 3 to 6 V AV+ = VDD AV- = VSS AV- AV+, AV- AD0 to AD7 Including the output off leakage current. VAIN = VDD Analog port input current IAIN VAIN = VSS When PE1 has the open-drain specifications. When PE1 has the open-drain specifications. When PE1 has the open-drain specifications. Figure 8 Figure 8 When PE1 has the open-drain specifications. When PE1 has the open-drain specifications. When PE1 has the open-drain specifications. Figure 8 Figure 8 VDD = 2.2 to 6 V WDR WDR WDR WDR WDR VDD = 2.2 to 6 V WDR WDR WDR 40 14 100 1% s ms 100 31 0.047 5% 680 1% 100 1% s ms F k AD0 to AD7 (The I/O shared function ports have opendrain specifications.) WDR WDR 99 (TCYC = 3.84 s) 195 (TCYC = 3.84 s) AV- VSS 200 AV- 500 Symbol Conditions Applicable pins and notes Ratings min typ 8 1 2 312 (TCYC = 12 s) 612 (TCYC = 12 s) VDD AV+ 800 AV+ 1 A -1 V A V max Unit bit LSB s
A/D converter characteristics
Conversion time
TCAD
Input reference voltage Input reference current range Analog input voltage range
AV+ AV- IRIF VAIN
Cw Recommended constants*10 Rw RI Watchdog timer Clear time (discharge) Clear period (charge) tWCT tWCCY Cw Recommended constants*10 Rw RI Clear time (discharge) Clear period (charge) tWCT tWCCY
0.1 5% 680 1%
F k
Notes:1. Allowed up to the amplitude generated when the oscillator shown in figure 3 is used with the recommended circuit constants and driven by the IC. 2. The average over a 100 ms period. 3. The operating VDD supply voltage must be maintained from the point the HALT instruction is executed until the IC has fully entered the standby state. Applications must also assure that no chattering occurs on the PA3 pin during the HALT instruction execution cycle. 4. Recommended circuit constants that have been verified to oscillate stably according to the oscillator element manufacturer using the Sanyostipulated oscillator characteristics evaluation board. 5. The OSC1 pin will have Schmitt characteristics when external clock oscillator is selected with the two-pin RC oscillator option. 6. These are the results of testing using our (Sanyo's) characteristics evaluation board with the recommended circuit constants used as external components. The current flowing in the IC's output transistors and transistors that have pull-up resistors is not included. 7. fCFOSC is the frequency when the recommended circuit constants from table 1 are used as external components. 8. Indicates the time required to achieve stable oscillation from the point VDD rises above the lower limit of the operating voltage range (See figure 4). 9. TCYC = 4 x the system clock period 10. If the application could be used in an environment in which condensation is possible, extra care with respect to the leakage between PE1 and adjacent pins and leakage associated with external resistors and capacitor is required during design.
No. 6278-32/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
External clock
open
0.15 VDD
Figure 1 External Clock Input Waveform
Ceramic oscillator element
Figure 2 Two-Pin RC Oscillator Circuit
Figure 3 Ceramic Oscillator Circuit
No. 6278-33/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Lower limit for the operating supply voltage
Stable oscillation Oscillation stabilization time tCFS
Figure 4 Oscillation Stabilization Time
Table 1 Recommended Ceramic Oscillator Circuit Constants
4 MHz (Murata Mfg. Co., Ltd.) CSA4.00MG CST4.00MGW (Internal capacitor) 4 MHz (Kyocera Corporation) KBR4.0MSA KBR4.0MKS (Internal capacitor) 1 MHz (Murata Mfg. Co., Ltd.) CSB1000J C1 C2 R C1 C2 R C1 C2 R 800 kHz (Murata Mfg. Co., Ltd.) CSB800J C1 C2 R 400 kHz (Murata Mfg. Co., Ltd.) CSB400P C1 C2 R 33 pF 10% 33 pF 10% 0 33 pF 10% 33 pF 10% 0 100 pF 10% 100 pF 10% 3.3 k 100 pF 10% 100 pF 10% 3.3 k 220 pF 10% 220 pF 10% 3.3 k Note: If the power supply rise time is zero, the reset time when CRES = 0.1 F will be between 10 and 100 ms. If the power supply rise time is long, increase the value of CRES so that the reset time is at least 10 ms.
Figure 5 Reset Circuit
No. 6278-34/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L
Input data
Load circuit
Output data
Figure 6 Serial I/O Timing
The load conditions are the same as those in figure 5.
Figure 7 Port PE0 Pulse Output Timing
tWCCY: tWCT:
The charge time due to the time constant of the circuit consisting of the external components Cw, Rw, and Rl. The discharge time due to software processing.
Figure 8 Watchdog Timer Waveform
No. 6278-35/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L RC Oscillator Characteristics for the LC651154L and LC651152L Figure 9 shows the RC oscillator characteristics for the LC651154L and LC651152L. However, the sample-to-sample variation in the LC651154L and LC651152L RC oscillator frequency described below does occur. 1) When: VDD = 2.2 to 6.0 V, Ta = -40 to +85C External constants: Cext = 270 pF Rext = 12.0 k fMOSC will be: 290 kHz fMOSC 841 kHz Therefore, only the above circuit constants are recommended. If use of circuit constants other than the above is unavoidable, they must be in the following ranges. Cext = 150 to 390 pF Rext = 3 to 20 k (See figure 9.) Note 8. The oscillator frequency must be in the range 350 to 850 kHz when VDD = 5.0 V and Ta = 25C. Note 9. Applications must be designed to have adequate margins so that the oscillator frequency falls in the operating clock frequency range (see the oscillator divider option table) for the voltage range VDD = 2.2 to 6.0 V and for the temperature range Ta = -40 to 85C.
These characteristics curves are for reference purposes only and are not guaranteed.
Figure 9 RC Oscillator Frequency Data (Representative Values)
No. 6278-36/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L Notes on Printed Circuit Board Design This section describes points that require care concerning noise from the point of view of the microcontroller and presents means of preventing associated problems when designing a printed circuit board to use with these products in a mass produced end product. The ideas presented in this section are effective design techniques for preventing and avoiding problems (such as incorrect microcontroller operation and program failures) due to noise. 1. The VDD and VSS power supply pins Insert capacitors that meet the following conditions between the VDD and VSS power supply pins. * The lengths of the lines between the VDD and VSS pins and the capacitors C1 and C2 should be as close to exactly equal as possible (L1 = L1', L2 = L2'). Furthermore, these distances should be as short as possible. * Insert two capacitors, C1 and C2 in parallel, with C1 having a large capacitance and C2 having a small capacitance. * The VDD and VSS lines in the printed circuit board pattern should be wider than any other lines in the pattern.
2. The OSC1 and OSC2 clock I/O pins -- If the ceramic oscillator option is selected (See figure 2-1.) * Keep the lines between the clock I/O pins (input: OSC1, output: OSC2) and the external components as short as possible (the distance Losc in the figure). * Make the length of the lines (Lvss + L1 and Lvss + L2) from the microcontroller VSS pin to the VSS side of the capacitors connected to the oscillator element as short as possible. * VSS line for the oscillator circuit and other VSS line should branch from a point nearest to the VSS pin. * Due to the capacitances of the wiring on the printed circuit board, it may be necessary to modify the values of the oscillator circuit constants (including the values of the capacitors C1 and Figure 2-1 Sample Oscillator Circuit 1 C2 and the limiting resistor Rd) from the values presented in (Ceramic oscillator) this catalog. We recommend consulting the manufacturer of the oscillator element with regard to these circuit constants. -- If the 2-pin RC oscillator option is selected (Figure 2-2) * Keep the lines between the clock I/O pins (input: OSC1, output: OSC2) and the external components (the capacitor Cext and the resistor Rext) as short as possible (the distance Losc in the figure). * Make the length of the lines (Lvss + Lc) from the microcontroller V SS pin to the V SS side of the capacitor functioning as the oscillator element as short as possible. * Take the VSS used by the oscillator circuit (as well as other VSS usages) from a point as close as possible to the VSS pin. Figure 2-2 Sample Oscillator Circuit 2 -- If the external oscillator option is selected (Figure 2-3) * Keep the line between the clock input pin (OSC1) and the external (2-pin RC oscillator) oscillator circuit as short as possible (the distance Losc in the figure). * Leave the clock output pin (OSC2) open. * Make the length (Losc) of the lines to the VDD and VSS pins used by the external oscillator as short as possible. -- Other points that apply to all oscillator circuits: External * Keep all lines that carry signals that change rapidly, signals that oscillator have large amplitudes due to being connected to the mediumvoltage handling capacity ports, or signals that carry large currents as far away from the oscillator circuit as possible. Also, do not allow such signal lines to cross any clock-signal related lines. Figure 2-3 Sample Oscillator Circuit 3 (External oscillator)
No. 6278-37/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L 3. RES: Reset pin * Keep the length of lines (Lres in the figure) from the RES pin to external circuits as short as possible. * Keep the length of the lines (L1 and L2) to the capacitor (Cres) inserted between RES and VSS as short as possible.
External circuit
Figure 3 RES Pin Wiring 4. TEST: Test pin * Keep the length of the line (L) from the TEST pin to the VSS pin as short as possible. * Run the line from the TEST pin to the VSS pin as close to the VSS pin as possible.
Figure 4 TEST Pin Wiring 5. AD0 to AD7: Analog input pins Analog input pin lines, such as those used to connect to an A/D converter input pin or a comparator input pin should be connected so as to meet the following conditions. * Keep the line (L1) between the limiting resistor (Rl) and the analog input pin as short as possible. * Locate the capacitor inserted between the analog input pins and the AV- pin (the A/D converter reference voltage input pin) as close as possible to the AV- input pin. That is, make the line length L1 + L2 as short as possible.
Analog input pin
External circuit (sensor block)
Figure 5 Analog Input Pin Wiring 6. I/O pins All of the pins on these products function as both input and output pins. * When used as an input pin, insert a limiting resistor, and keep the length of the line to that pin as short as possible. Supplement: This is not only useful in printed circuit board design, but is also useful in preventing and avoiding problems (such as incorrect microcontroller operation and program failures) by taking the program specifications and microcontroller option selections described below into consideration. * If signals are input from external sources when the microcontroller power supply is unstable, select the mediumvoltage handling capacity (n-channel open drain) output as the output type option for that input pin, and also insert a limiting resistor in the input circuit. * Always implement key chattering exclusion measures for external signals applied to microcontroller input pins. * The pin output data should be re-output periodically with an output instruction (OP or SPB).
No. 6278-38/39
LC651154N, 651154F, 651154L, 651152N, 651152F, 651152L * When reading data input to a pin that can function as either input or output, set the output value for that pin to 1 every time the input is read using an output instruction (OP or SPB). 7. Unused pins * See the users manual for the product or refer to the pin functions as described in the semiconductor report for the device.
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of September, 1999. Specifications and information herein are subject to change without notice. PS No. 6278-39/39

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